The present invention relates to electronics and electronic circuits. More specifically, the present invention relates to amplifier circuits and operational amplifiers.
More specifically, the present invention relates to a full differential operational amplifier circuit having differential feedback stages rejecting common mode signals at the output of the differential operational amplifier. Heretofore operational amplifiers circuits have been designed in a wide variety of configurations and fabricated by a wide variety of process technologies.
A well known operational amplifier is the full differential amplifier having a positive differential input and a negative differential input and having a positive differential output and a negative differential output. The voltage potential difference between the two inputs is amplified and presented as a differential output signal between the two differential outputs of the full differential amplifier.
One of the most significant uses of the differential amplifier is controlled amplification through negative feedback. Negative feedback occurs when an output signal of the amplifier is fedback to the negative input. Negative feedback of the differential operational amplifier provides for predictable controlled closed loop amplification over the bandwidth of the amplifier.
The designers of operational amplifiers have continually strived for better performing amplifiers. Input offset currents, input offset voltages, bandwidth, gain, input impedance, output impedance, inter alia, are parameters that are considered by those who select differential amplifiers for particular applications. Gain and bandwidth are the two most commonly considered parameters. As the gain of the differential operational amplifiers increases, the circuit using a differential operational amplifier with negative feedback, become more precise and predictable. The higher the bandwidth, the higher the operating frequency. The gain-bandwidth product is a combined parameter of usefulness of an amplifier. These and other parameters are defined by the inherent design of the amplifier.
Typical full differential amplifier designs include a differential input stage, which is a gain stage, connected to a pair of output gain stages each providing a respective differential output. A large compensation capacitor is dispose between the differential input stage and each of the two output gain stages.
The gain of the differential amplifier is the product of the gain of the differential input stage multiplied by the gain of the output gain stage. The gain for conventional two micron linear CMOS amplifiers may be approximately fifty thousand. Each output gain stage is typically followed by a respective follower output stage. The buffering output stages provide the amplifier differential outputs with a low output impedance desired in many circuit applications.
As examples of other full differential amplifiers, the TL592 and TL592A "Differential Video Amplifier" manufactured by TEXAS INSTRUMENTS, and the NE592 and SE592 "Video Amplifier" manufactured by SIGNETICS, are full differential amplifier characterized by amplification provided by two cascaded gain stages between the differential inputs and the differential outputs.
Three different operational amplifiers, two in CMOS technology and the other in bipolar technology, having differential inputs stages, compensation capacitors and outputs gain stages having conventional designs are disclosed in U.S. Pat. No. 4,464,588 (hereinafter 588), U.S. Pat. No. 4,383,223 (hereinafter 223) and U.S. Pat. No. 4,477,780, (hereinafter 780) all of which are here incorporated by reference as there fully setforth. Differing process technologies, for examples CMOS and bipolar, may use substantially similar designs
U.S. Pat. No. 223 discloses a CMOS operational amplifier having conventional current mirror loads in the input differential stage, and an output push-pull stage with a compensation capacitor connected therebetween. U.S. Pat. No. 588 discloses a CMOS amplifier having the positive input connected to a ground reference and having its output negatively fedback to the negative input thereby forming a voltage reference circuit.
U.S. Pat. No. 780 discloses a bipolar amplifier with multiple output follower stages each of which is negatively fedback to the negative input with the positive input connected to a ground reference thereby forming a multiple voltage reference circuit. Though the applications of the operational amplifier may be different, all three circuits include a conventional operational amplifier having a differential input stage, a compensation capacitor and an output gain stage.
The compensation capacitor between the two gain stages produces an increasing gain attenuation above a predetermined frequency which is substantially lower than the natural frequency of the operational amplifier, at which natural frequency the amplifier obtains additional 180 phase shift between its inputs and its outputs. A 180 degrees of phase shift of the negative feedback connection when added to the additional 180 of phase shift associated with the natural frequencies, can cause the amplifier to become unstable and oscillate by virtue of positive feedback associated with 360 degrees of phase shift between the inputs and the outputs.
The gain attenuation caused by the compensation capacitor is so severe at the high natural frequency of the amplifier, that the gain of the amplifier is substantially less than one so that only a portion of the output signal is positively fedback thereby preventing unstable oscillations.
In classical two stage amplifiers, the compensation capacitor is positioned between the two gain stages perfecting a Miller effect. The Miller effect, enabled by feedback through the capacitor from the output of the output gain stage to the output of the input stage, provides equivalent capacitive compensation corresponding to the gain of the first stage multiplied by the capacitance of the compensation capacitor. This multiplication factor reduces the required capacitance thereby reducing the size of a corresponding compensation capacitor. Miller effect compensation techniques are generally well known in the art.
U.S. Pat. No. 223 discloses a compensation capacitor twenty. U.S. Pat. No. 877 discloses a compensation capacitor twenty six. U.S. Pat. No. 780 discloses compensation capacitor fourteen. Even though the Miller effect reduces the size of the compensation capacitor, sufficient compensation still requires relatively large capacitance correspondingly requiring large semiconductor area and therefore decreases the yields and increases the cost of semiconductor devices. Also, the capacitors, as they are intended to do, decrease the bandwidth of the amplifier, for example, to five megahertz.
Moreover, large capacitors tend to pass large currents which in turn require more power for a power source thereby dissipating more power in the amplifier device. Conventional CMOS amplifiers, for example, the NE592 linear CMOS amplifier dissipates approximately 20 milliwatts.
The input differential stage generally includes two coupled transistors connected to a current source drawing a constant current through the coupled transistors. The sum of the current through each equals the constant current. The current through the coupled transistors will generally follow a hyperbolic tangent curve permitting rapid current change with little voltage change at the inputs of the transistors providing a high voltage to current conversion in the input differential stage.
A modern means of obtaining a constant current is by use of well known current mirrors. Typically, in a current mirror, a constant current is established in a current path transistor through a stacked resistor both connected in series between power supply references. The current which flows therethrough is generally equal to the difference between the power supply references divided by the sum of resistances of the resistor and the current path transistor. A mirror transistor is then connected to the current path transistor, such that both transistors conduct the same amount of current. A conducting terminal of the mirror transistor then acts as a constant current source varying its transconductance to maintain the constant current therethrough.
An improved current mirror is the feedback current mirror commonly known as the Wilson current mirror. A commercially available part manufactured by TEXAS INSTRUMENTS called the TL010I or TL010C "Adjustable-Ratio Current Mirrors" comprises a plurality of Wilson current mirror circuits.
U.S. Pat. No. 588 discloses a feedback current mirror comprising transistors twenty nine, thirty and thirty one. Transistor thirty one has a gate terminal which is fedback and connected to the input transistor twenty nine. The feedback connection and the use of transistor thirty one improves the performance of the current mirror by reducing second order effects of output voltages of the current mirror which effect disadvantageously change the current in a constant current mirror.
U.S. Pat. No. 588 also discloses conventional current mirrors, for example, the circuit comprising transistors thirty three and seventeen, and, for example, the circuit comprising transistors eighteen and nineteen.
U.S. Pat. No. 223 has a conventional current source comprising transistor six providing constant current to coupled transistors eight and twelve. Also, transistors ten and fourteen therein form a conventional current mirror load of the coupled transistors providing a voltage output characterized by large voltage fluxion.
U.S. Pat. No. 780 discloses two emitter coupled PNP transistors eleven and twelve, connected to a fifteen microampere constant current source. U.S. Pat. No. 588 discloses source coupled P channel MOS transistors connected to a constant current source providing a constant current I. U.S. Pat. No. 588 has a current mirror comprising current path transistors twenty eight and twenty nine, establishing a constant current through transistors thirty three, thirty two and thirty, which constant current is then established in a mirror transistor seventeen drawing a constant current through coupled transistors fourteen and fifteen. These are common current mirror arrangements.
All three circuits of U.S. Pat. Nos. 223, 780 and 588 have mirror current loads in the input differential stage for providing voltage gain in the input differential stage. For example, in U.S. Pat. No. 588, transistor nineteen reflects the current in transistor eighteen, and transistor nineteen provides for high voltage gain at its drain terminal by virtue of a high impedance into that drain terminal.
Some input differential stages provide for voltage to current amplification using current mirror active loads. For example, a current mirror load having a first and a second MOS transistor having their source connected to a positive power source, having their gate terminals connected together and connected to the output of an input transistor, while the drain of the first transistor is also connected to output terminal of the input transistor.
The drain terminal of the second transistor acts as a current source at its drain terminal reflecting the current in the first transistor which in turn reflects the current through the input transistor. Hence, a voltage change at the gates of the input transistors produces a current reflection at the drain output of the second transistor.
One problem associated with this voltage to current reflection configuration of the input differential stage using CMOS current mirror active loads, is the second order effect of small signal voltage levels at the drain terminal of the second transistor, which drain terminal acts as a current source driving other cascaded circuits. The second order effect of a small signal voltage superimposed at the output of the second transistor causes a corresponding fluxion of the output current by virtue of the output transistors having a drain current versus drain to source voltage curve which has a slope corresponding to an output impedance. More simply, a change in output voltage of this current source causes a change in the current value. This change in current does not occur in ideal current sources.
This second order effect slows down the operation of the input differential stage because the current mirror load requires time to react to the superimposed voltage change causing an unwanted temporary change in the output current.
Another problem associated with two stage voltage gain amplifiers are parasitic effects in which large varying voltage signals produce current flow in parasitic capacitance thereby reducing the bandwidth of the amplifier. Hence, amplifiers which operate on internal voltage signals with large amplitude variation tend to have lower slew rates and bandwidths.
Some input differential amplifiers stages have been connected to CMOS cascode output stages which provide high gain and which typically comprises four transistors stacked vertically between a positive voltage reference and a negative voltage reference. The top and bottom transistors act as signal transistors while the middle two act as pass transistors. The two pass transistors have their gate terminal connected to a bias reference voltage and pass a signal from a respective signal transistor to the output at the connection between the two pass transistors. The two signal transistors have their gate terminals connected to two differential voltage signals.
One problem associated with the use of pass transistors in the cascode stage is the presence of two transistors between the output and a power reference thereby limiting the dynamic range of the amplifier output voltage signal. Consequently, for CMOS technology, the amplifiers typically require an additional high voltage power supply in a five volt logic system.
Another problem associated with the use of pass transistors in the cascode stage is that the bias is fixed to a voltage reference thereby preventing variable bias. The slew rates and settling time of high speed signals are limited by slow fixed bias pass transistors. Conventional two stage amplifiers with large voltage fluxion using fixed bias pass transistors in the cascode stage typically have slow slew rates of ten volts per microsecond and slow one percent settling times of 300 nanoseconds, for example, in response to a two volt step.
One of foremost problems associated with full differential operational amplifiers having differential outputs, is superimposed common mode signals upon the differential output signals. Heretofore solutions to the superposition of the common mode signals has been to design the full differential amplifiers with precision components providing open loop rejection. However, these solutions do not provide for operative closed loop rejection of the common mode single, which rejection is far superior to the open loop common mode rejection by virtue of the dynamic negative feedback providing controlled operations continued through the operating frequency range of the amplifiers.
Though heretofore designs of conventional operational amplifiers were improvements over previous designs, those skilled in the art strive ever more to yet further improve upon those designs. The foregoing amplifiers having the corresponding disadvantages or design limitations are further improved upon using teachings of the present invention.